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1 typical a pplica t ion fea t ures descrip t ion 18v dual input micropower powerpath prioritizer the lt c ? 4419 is a dual input monolithic powerpath? prioritizer with low operating current, that provides backup switchover for keeping critical circuitry alive during brown out and power loss conditions. unlike diode-or products, little current is drawn from the inactive supply even if its voltage is greater than the active supply. internal 2, current limited pmos switches provide power path selection from a primary input (v1) or a backup input (v2) to the output. an adjustable voltage monitor set via an external resistive divider provides flexibility in setting the v1 to v2 switchover threshold. when primary input v1 drops, the adj monitor input causes out to be switched to v2. fast non-overlap switchover circuitry prevents both reverse and cross conduction while minimizing output droop. the ltc4419 has two auxiliary comparators with open- drain outputs that provide flexible voltage monitoring. the v2on output indicates if v2 is powering out. freshness seal mode prevents v2 battery discharge during storage or shipment. a pplica t ions n selects highest priority valid supply from two inputs n wide 1.8v to 18v operating range n internal dual 2, 0.5a switches n low 3.6a operating current n low 320na v2 current when v1 connected to out n blocks reverse and cross conduction currents n reverse supply protection to C15v n v2 freshness seal/ship mode n 1.5% accurate adjustable switchover threshold n two auxiliary 2.3% accurate voltage comparators n overcurrent and thermal protection n thermally enhanced 10-pin 3mm 3mm dfn and 12-lead exposed pad msop packages n low power battery backup n portable equipment n point-of-sale (pos) equipment l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. + 1m 1m v2on 1m 5v wall adapter 237k c1 10f 121k 4.02m 7.4v li-ion 280k v1 out out v1uv v2uv cmpout1 cmpout2 v2on adj cmp1 cmp2 4419 ta01a switchover threshold: v1 < 4v (v1 falling) gnd ltc4419 v2 v2uv threshold: v2 < 6v (v2 falling) v1uv threshold: v1 < 4.4v (v1 falling) typical switchover waveforms lt c4419 4419f for more information www.linear.com/ltc4419 4419 ta01b switchover threshold c out = 10f i load = 100ma out 50s/div v2 2v/div v1 2v/div
2 a bsolu t e maxi m u m r a t ings input supply voltage v1 , v2 ...................................................... C 15v to 24v out ....................................................... C0. 3v to 24v out C v2 .................................................C 24v to 39v out C v1 ................................................. C 24v to 39v input voltages ad j , cm p1 , cm p2 ( note 3 ) .................. C 0. 3v to 24v output voltages cm pout1 , cmpout2 , v2 on ( note 3 ) .. C 0. 3v to 24v (notes 1, 2) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4419cdd#pbf ltc4419cdd#trpbf lgms 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc4419idd#pbf ltc4419idd#trpbf lgms 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc4419cmse#pbf ltc4419cmse#trpbf 4419 12-lead plastic exposed pad msop 0c to 70c ltc4419imse#pbf ltc4419imse#trpbf 4419 12-lead plastic exposed pad msop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. top view 11 gnd dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 v2 cmp2 out v2on cmpout2 v1 cmp1 adj gnd cmpout1 t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 6 v1 nc cmp1 adj gnd cmpout1 12 11 10 9 8 7 v2 nc cmp2 out v2on cmpout2 top view 13 gnd mse package 12-lead plastic msop t jmax = 125c, ja = 40c/w exposed pad (pin 13) is gnd, must be soldered to pcb p in c on f igura t ion pin currents ( note 2 ) ad j , cm p1 , cm p2 , cmpout1 , cmpout2 , v2 on ................................................................. C 1m a operating ambient temperature range lt c4 419 c ................................................ 0 c to 70c lt c4 419 i ............................................. C 40 c to 85c junction temperature ( notes 4 , 5) ........................ 125 c storage temperature range .................. C 65 c to 150c lead temperature ( soldering , 10 sec ) ms op package ................................................. 30 0 c (http://www .linear.com/product/ltc4419#orderinfo) lt c4419 4419f for more information www.linear.com/ltc4419
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v1 = 3.6v, v2 = 3.6v unless otherwise noted. symbol parameter conditions min typ max units supply voltage and currents v1, v2 operating voltage range l 1.8 18 v i v1 v1 current, v1 powering out v1 current, v2 powering out i out = 0, v1 = 8.4v, v2 = 3.6v v1 = 8.4v, v2 = 3.6v l l 3.6 500 6 .3 800 a na i v2 v2 current, v2 powering out v2 current, v1 powering out v2 current in freshness seal mode i out = 0, v1 = 3.6v, v2 = 8.4v v1 = 3.6v, v2 = 8.4v v1 = gnd, v2 = 5v l l l 3.3 320 120 6 650 220 a na na r on switch resistance v1 = v2 = 5v, i out = C100ma l 1 2 5 t valid(v1) input qualification time v1 rising, adj rising l 34 64 94 ms input comparators v tha adj threshold adj falling l 1.032 1.047 1.062 v v hysta adj comparator hysteresis adj rising l 30 50 70 mv v thc cmp1, cmp2 threshold cmp1, cmp2 falling l 0.378 0.387 0.396 v v hystc cmp1, cmp2 hysteresis cmp1, cmp2 rising l 7.5 10 12.5 mv t pda adj comparator falling response time 10% overdrive l 4 7.3 12 s t pdc cmp1, cmp2 comparator response times 20% overdrive l 30 65 s power path function i lim output current limit v1, v2 = 8.4v l 0.5 1.1 1.6 a v rev reverse comparator threshold (v1, v2) C v out for power path turn-on l 25 50 75 mv t switch break-before-make switchover time v1 = v2 = 5v, i out < C10ma l 1 2.5 5 s i/o specifications v ol output voltage low, cmpout1, cmpout2 and v2on i = 100a i = 1ma l l 15 120 50 250 mv mv v oh v2on output high voltage i = C1a, v2 = 5v l 1.05 1.65 2.3 v i oh cmpout1, cmpout2 and v2on, output high leakage cmpout1 , cmpout2, v2on = 18v l 50 150 na i pu(v2on) v2on pull-up current v2 = 5v, adj = 0v, v2on = 0v l C2.7 C5 C8 a i leak adj, cmp1, cmp2 leakage current adj, cmp1, cmp2 = 0v, 1.5v l 1 5 na note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3: these pins can be tied to voltages down to C5v through a resistor that limits the current to less than C1ma. note 4: the ltc4419 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 5: the ltc4419 is tested under pulsed load conditions such that t j t a . the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) lt c4419 4419f for more information www.linear.com/ltc4419
4 typical p er f or m ance c harac t eris t ics v1 current, v2 powers out normalized falling adj threshold vs temperature normalized cmp1 and cmp2 falling thresholds vs temperature adj hysteresis vs temperature v1 current, v1 powers out (i out = 0) v2 current, v2 powers out (i out = 0) v2 current, v1 powers out open-drain (cmpout1, cmpout2, v2on) v ol vs pull-down current adj leakage vs temperature (t a = 25 c, v1 = v2 = 3. 6v unless otherwise indicated ). lt c4419 4419f for more information www.linear.com/ltc4419 50 125 0.990 0.995 1.000 1.005 1.010 normalized v thc 4419 g06 temperature (c) ?50 75 ?25 0 25 50 75 100 125 30 40 50 100 60 70 adj hysteresis (mv) 4419 g08 pull-down current (ma) 0.0 0.5 1.0 1.5 2 125 0 50 100 150 200 250 v ol (mv) 4419 g05 v adj = 0v, 1.5v temperature (c) 2.5 ?50 ?25 0 25 50 75 100 125 0.5 1.0 3.0 1.5 2.0 2.5 3.0 adj leakage (na) 4419 g09 3.5 4.0 4.5 4419 g01 v1 = 1.8v v1 current (a) v2 = 1.8v v2 = 3.6v v2 6v temperature (c) ?50 ?25 0 25 50 v1 = 3.6v 75 100 125 2.5 3.0 3.5 4.0 4419 g02 v2 current (a) v1 = v2 v1 6v ?40c 25c 85c v2 voltage (v) 0 5 10 15 20 150 temperature (c) 200 250 300 350 400 450 v2 current (na) 4419 g03 v1 = v2 ?40c ?50 25c 85c v2 voltage (v) 0 5 10 15 20 300 350 ?25 400 450 500 550 4419 g04 v1 current (na) temperature (c) ?50 ?25 0 0 25 50 75 100 125 0.990 0.995 1.000 1.005 1.010 25 normalized v tha 4419 g07 temperature (c) ?50 ?25 0 25 50 75 100
5 output voltage and current waveforms during switchover output current i out response for different shorting impedances typical p er f or m ance c harac t eris t ics output current limit vs temperature i out vs v out for different input supply voltages v1 reverse voltage blocking with v2 powering out switchover from a higher to a lower voltage switch r on vs temperature (t a = 25 c, v1 = v2 = 3. 6v unless otherwise indicated ). freshness seal current vs v2 voltage and temperature lt c4419 4419f for more information www.linear.com/ltc4419 2v/div 40 s/div 0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) 4419 g11 4419 g16 v1 = 0v 1.8v 3.6v 5v 6v temperature (c) ?50 ?25 0 25 c out = 10f c1 = c2 = 10f i load = 50ma 50 75 100 0 50 100 150 200 250 4419 g14 5v v2 current (na) 3.6v 2v temperature (c) ?50 ?25 0 out 25 50 75 100 125 1 2 3 4 5 10v r on () 4419 g13 temperature (c) ?50 ?25 0 25 50 75 100 6v 125 0.80 0.90 1.00 1.10 1.20 1.30 1.40 current limit (a) 4419 g10 10s/div i load = 50ma 6v ?10v 10v 20ms/div v2 5v/div v1 10v/div i out v2 0.5a/div 4419 g17 ohmic current limit foldback v in = 1.8v v in = 3.6v v in = 5v v out (v) i out 0 1 2 3 4 5 0 0.2 0.4 0.6 0.5a/div 0.8 1.0 1.2 i out (a) 4419 g12 c out = 10f i out = 200ma disconnect from v1 connect to v2 3ms/div v1 v1 out 2v/div v2 4419 g15 1.2 2.2 3.3 3.9 5.0
6 p in func t ions adj: adjustable v1 switchover threshold input. adj is the noninverting input to the switchover threshold comparator. if v1 1.55v and adj 1.097v for at least 64ms, out is switched internally to the primary v1 input. when the adj input voltage is lower than 1.047v, out is switched internally to v2, if v2 1.55v. otherwise, out stays unpowered. tie adj via a resistive divider to v1 to set the v1 to v2 switchover voltage. do not leave open. cmp1: auxiliary comparator 1 monitor input. cmp1 is the noninverting input to an auxiliary comparator . the invert - ing input is internally connected to a 0.387v reference. connect cm p1 to gnd when it is not used. cmp2: auxiliary comparator 2 monitor input . cmp2 is the noninverting input to a second auxiliary comparator . the inverting input is internally connected to a 0.387v reference. connect cmp2 to gnd when it is not used. cmpout1: auxiliary comparator 1 output . this open-drain comparator output is pulled low when cm p1 is below 0.387v and during power-up, otherwise it is released. once released, connecting a resistor between cmpout1 and a desired supply voltage up to 18v causes this pin to be pulled high. leave open if unused. cmpout2: auxiliary comparator 2 output . this open-drain comparator output is pulled low when cm p2 is below 0.387v and during power-up, otherwise it is released. once released, connecting a resistor between cmpout1 and a desired supply voltage up to 18v causes this pin to be pulled high. leave open if unused. exposed pad: for best thermal performance, solder ex - posed pad to a large pcb area. gnd: device ground. nc: no connection. not internally connected. out: output voltage supply. out is a prioritized voltage output that is either connected to v1, v2 or is unpowered as indicated in table 1 of the applications information section. additionally, out must be at least 50mv below the input supply for a connection to that supply to be activated. bypass with a capacitor of 1f or greater. see applications information section for bypass capacitor recommendations. v1: primary power supply. out is internally switched to v1 if v1 1.55v and adj 1.097v. when in freshness seal mode, applying v1 1.55v and adj 1.097v for 32ms disables freshness seal. bypass with 1f or greater. tie to gnd if unused. v2: backup power supply . v2 is valid if its voltage is 1.55v. out is internally switched to v2 if adj < 1 .047v or v1 < 1.55v, provided v2 is valid. refer to table 1 of the applications information section. bypass with 1f or greater. tie to gnd if unused. v2on: v2 connected status . v2on is an output that is driven high with a 5a pull-up when the v2 to out power path is active. otherwise it is driven low. connect a resis - tor between out or v2 and this pin to provide additional pull-up . as this pin is used to enable freshness seal, do not force low or connect a pull-down resistor to this pin . leave open if unused. lt c4419 4419f for more information www.linear.com/ltc4419
7 func t ional diagra m + ? + ? 1.097v/ 1.047v cadj adj + ? 1.55v/ 1.52v cuv2 + ? 1.55v/ 1.52v cuv1 + ? crev2 64ms 7.3s 0.397v/ 0.387v cp2 cmp2 v2 v1 freshness seal 50mv out + ? + ? crev1 en1 en2 2.5v 5a 50mv out out cmpout2 + ? + ? 0.397v/ 0.387v cp1 cmp1 cmpout1 v2on control logic gnd 4419 fd lt c4419 4419f for more information www.linear.com/ltc4419
8 o pera t ion the functional diagram shows the major blocks of the ltc4419. the ltc4419 is a powerpath prioritizer that switches output out between primary (v1) and backup (v2) sources depending on their validity and priority with v1 having the highest priority. if neither supply is valid, out stays unpowered. a resistive divider between v1, adj and gnd and comparators cuv1 and cadj are used to monitor v1 s voltage to establish validity . v1 is valid if v1 1.55v and adj 1.097v for 64ms after v1 rises above 1.55v. otherwise v1 is invalid . v2 is valid if its voltage as monitored by comparator cuv2 is 1.55v. otherwise, it is invalid. switchover threshold is independent of relative v1 and v2 voltages, permitting v1 to be lower or higher than v2 when v1 powers out and vice versa. power connection to the output is made by enhancing back- to-back internal p-channel mosfets . current passed by the mosfets is limited to typically 1.1a if out is greater than 1v. otherwise it is limited to 250ma. when switching from v1 to v2, the v1 to out power path is first disabled and comparator crev2 is enabled. after the out voltage drops 50mv below v2, as detected by crev2, out is then connected to v2. v2on pulls high after switchover. this break-before-make strategy prevents out from backfeeding v2 . switchover back to v1 occurs in a similar manner once v1 has been revalidated . v2on pulls low if the v2 power path is disabled and during initial power-up when v1 or v2 is first applied. the ltc4419 blocks reverse voltages up to C15v when a reverse condition occurs on an inactive channel. the ltc4419 also disables a channel if the corresponding input supply falls below 1.52v. a small ~3a current is drawn from either the prioritized input supply or the highest input supply if both input supplies are below 1.55v. very little current (~320na) is drawn from the unused supply. the ltc4419 provides two additional comparators, cp1 and cp2, whose open-drain outputs pull low when cmp1 and cmp2 pin voltages fall below 0.387v and during initial power-up. these comparators can be used to monitor supplies to provide early power failure warning and other useful information. the ltc4419 can be put into a v2 freshness seal mode to prevent battery discharge during storage or shipment . the applications information section lists the steps to engage and disengage v2 freshness seal. lt c4419 4419f for more information www.linear.com/ltc4419
9 a pplica t ions i n f or m a t ion the ltc4419 is a low quiescent current 2-channel priori - tizer that powers both its internal circuitry and its output out from a prioritized valid input supply . unlike an ideal diode-or, the ltc4419 does not draw current from the highest supply as long as any one supply is greater than 1. 8v. table 1 lists the input supply from which the ltc4419 draws its internal quiescent current i cc and the supply to which out is connected after input supplies have been qualified. table 1. out and ltc4419 i cc power table input voltages out connection i cc source v1 > 1.55v adj > 1.097v v2 > 1.55v y ? y ? x v1 v1 x n y v2 v2 y n n hi-z v1 n x y v2 v2 n x n hi-z v max * note: x = dont care. *v max = higher of v1 and v2. ? for 64ms. a typical battery backup application is shown in figure 1 . v1 is powered by a 2- cell li-ion battery pack whose safe discharge limit is between 5.6v and 6v. v2 is powered by a 9v alkaline hold-up battery which is completely discharged when its voltage drops to 6v. in order to protect the 2-cell li-ion battery on v1, switchover threshold is set to ~5.6v. after switchover to v2, the li-ion battery primarily supplies only divider r1-r3s current, as the ltc4419 draws only a small standby current from v1. monitor inputs cmp1 and cmp2 are configured to provide v1 and v2 undervoltage + r3 1m r6 1m switchover threshold: v1< 5.6v (v1 falling) r7 1m c out 10f r2 150k r1 78.7k r4 280k r5 4.02m 9v alkaline + 2-cell 7.4v li-ion c1 4.7f v1 out out v2uv v1uv cmpout2 cmpout1 adj cmp1 cmp2 4419 f01 gnd ltc4419 v2 c2 4.7f v1uv : v1 < 6v (v1 falling) v2uv : v2 < 6v (v2 falling) warnings. outputs v1uv and v2uv are driven low when v1 and v2 voltages fall below 6v. relevant equations used to calculate these component values are discussed in the following subsections. setting the switchover threshold several factors affect switchover voltage and should be taken into account when calculating resistor values. these include resistor tolerance, 1.5% adj comparator threshold error, divider impedance and worst-case adj pin leakage. these factors also apply to resistive dividers connected to monitor inputs cmp1 and cmp2. referring to figure? 1 and the electrical characteristics table, the typical v1 switchover threshold is: v sw1 = v tha r1 + r2 ? r1 + r2 + r3 ( ) (1) t ypical v1 undervoltage threshold is: v v1uv = v thc r1 ? r1 + r2 + r3 ( ) (2) and typical v2 under voltage threshold is: v v2uv = v thc r4 ? r4 + r5 ( ) (3) equations 1-3 assume adj and cmp pin leakages are negligible. to account for pin leakage, equations 1-3 must be modified by an i leak ? r eq term, where equivalent resistance, r eq , must be calculated on a case-by-case basis. worst-case component values and reference voltage tolerances must be used to calculate the maximum and minimum threshold voltages. for example, to calculate minimum falling switchover threshold voltage, v sw1(min) , use v tha(min) , (r2 + r1) (max) , and r3 (min) in equation 1. selecting output capacitor, c out c out can be selected to control either output voltage droop during switchover or output rising slew rate during initial power-up or when switching to a higher supply. in general, output droop, ?v out , can be calculated by: ? v out = t nov ? i out c out (4) figure?1. the ltc4419 protecting a 2-cell li-ion battery pack on v1 from discharge below its safe minimum voltage lt c4419 4419f for more information www.linear.com/ltc4419
10 where i out is the current supplied by c out during non- overlap or dead time t nov . choosing: c out t nov ? i out ? v out (5) limits output droop to less than ?v out . in order to estimate t nov and i out , first consider a scenario where power supplies are present on both v1 and v2, and their voltages are changing slowly compared to the adj comparator propagation delay t pda . in such cases, i out is i load and t nov is t switch . c out can be sized according to equation 5 with i out = i load(max) and t nov = t switch(max) to limit maximum output droop when switching to a higher supply. when switching to a lower supply, switchover is initiated only after out falls v rev below the supply that is being switched in. in such cases, total output droop is ?v out + v rev . next consider a scenario where the input power source powering out is unplugged. out back-feeds circuitry connected to the input supply pin. both input and output droop at the same rate. referring to figure 1, assume the battery on v1 is unplugged when out is connected to v1. i out is the sum of i load and the reverse current i back , which in this example is i r3 . as out and v1, since the two are connected, droop below the adj threshold, switchover occurs to v2 with a dead time: t nov = t pda + t switch (6) where t pda is an overdrive dependent adj comparator delay. as an approximation, use t pda from the electrical characteristics table to estimate t nov . use this t nov and: i out = (i back + i load ) (7) in equation 5 to size c out : c out t pda + t switch ( ) ? i out ? v out (8) refer to figure 2 for a more accurate estimate of t pda versus dv out /dt. if adj is filtered with capacitor, its discharge time via divider r1-r3 increases t pda . this results in a higher output droop than estimated by equation 8. a pplica t ions i n f or m a t ion in order to limit output rising slew rate dv out /dt, size: c out i lim dv out dt (9) as the ltc4419 limits out charging current to i lim until out approaches the input supply to within i lim ? r on , where r on is the channel switch resistance. refer to the thermal protection and maximum c out section to deter - mine maximum allowed c out . inductive effects parasitic inductance and resistance can impact circuit performance by causing overshoot and undershoot of input and output voltages depending on the scenario . para - sitic inductance in the power path causes positive-going overshoot on the input and a negative-going undershoot on the output when the ltc4419 turns off. another cause of positive input overshoot is r-l-c tank ringing during hot plug of an input supply. input overshoot is most pro - nounced when the total resistance of the input tank is low . care must be taken to ensure overvoltage transients do not exceed the absolute maximum ratings of the ltc4419. additionally, parasitic resistance and inductance can cause input undershoot during power path turn-on. if severe enough, undershoot can temporarily invalidate a supply and cause repeated power up cycles (motorboating) or unwanted switchover between sources. figure?2. adj comparator propagation delay as a function of slew rate; t pda vs dv adj /dt lt c4419 4419f for more information www.linear.com/ltc4419 50 75 100 125 t pda (s) 4419 f02 dv adj /dt (v/s) 10 100 1k 10k 100k 0 25
11 a pplica t ions i n f or m a t ion the first step to avoid these issues is to minimize parasitic inductance and resistance in the power path. guidelines are given in the layout section for minimizing parasitic inductance on the printed circuit board (pcb). external to the pcb, twist the power and ground wires together to minimize inductance. second, use a bypass capacitor at the input to limit input voltage overshoot during ltc4419 power path turn off. a few micro farads is sufficient for most applications. when hot plugging supplies with large parasitic inductances, it is possible for the r-l-c tank to ring to more than twice the nominal supply voltage. wall adapters and batteries typically have enough loss (i.e. series resistance) to prevent ringing of this magnitude . however, if this is a problem, snub input capacitor c sn1 with resistor r sn1 , typically 0.5. place this network close to the supply pin. third, if an input capacitor is not permissible, use a tvs (such as smaj16ca) in applications when supply pin transients can exceed 24v. use a bidirectional tvs in applications requiring reverse input protection. note that a tvs does not address droop and motorboating , which are solved only by input bypassing. during normal operation, the ltc4419 limits power path current to < 1.6a and internal circuitry prevents out from ringing below ground during power path turn off. this is also true for output shorts when the short is close to the ltc4419s out pin. however, if the output is shorted through a long wire, current in the wire inductance (l par2 in figure 3) builds up due to the discharge of c out1 and can be much higher than 1.6a. this current causes the out pin to ring below its ?0.3v absolute maximum rating once c out1 has been fully discharged. for this special case, split the output capacitor between c out1 and c out2 and make c out1 small. snub c out1 with resistor r sn2 to damp r-l-c ringing if required. size c out2 to obtain the required total output capacitance. also add a diode between out and ground close to the ltc4419 to clamp negative ringing if the out pin rings below C0.3v. increasing cmp1 and cmp2 hysteresis in some applications, built-in cmp1 hysteresis may be insuf - ficient. in such cases , cmp1 hysteresis can be increased as shown in figure 4. hysteresis at the monitored input v mon with r8 present and assuming r9 << r8 is given by: v hyst = v hystc ? r3 r1||r3||r8 + v pu ? r3 r8 (10) where v hystc and v thc are found in the electrical character - istics table and are typically 10mv and 0. 387v respectively . account for supply v pu and resistor r8 when calculating rising and falling thresholds of monitored input v mon . supply impedance and adj comparator hysteresis in some applications , v1 could be supplied by a battery pack with high esr or through a long cable with appreciable series resistance. load current, i out , flowing through this resistance reduces the monitored v1 voltage by: ?v1 = i out ? r esr (11) v1 out 4419 f03 c out1 1f d1 1n5818 c sn1 5f r sn1 0.5 l par1 optional l par2 out v1 ltc4419 r sn2 1 optional c out2 10f figure?3. recommended inductive transient suppression circuitry cmp1 v mon v pu ltc4419 r8 r3 r1 r9 cmpout1 4419 f04 figure?4. increasing cmp1 hysteresis lt c4419 4419f for more information www.linear.com/ltc4419
12 a pplica t ions i n f or m a t ion the drop can be as high as: ?v1 = i lim ? r esr (12) when c out is initially being charged. voltage droop at the v1 pin can result in repeated switchover between v1 and v2 if built-in v1 (adj) hysteresis is insufficient. in such cases , cm p1 can be used to set v1 hysteresis as shown in figure 5. when v1 falls, adj and cmp2 are pulled low when cm p1 falls below v thc and output cmpout2 activates hysteresis resistor r8. when switching from v1 to v2, current supplied by v1 will go to zero, result - ing in a voltage increase on v1. switchover back to v1 is prevented due to increased v1 hysteresis as determined by equation 10. v1 droop is higher during the initial charging of c out . referring to figure 5, to prevent repeated switchover when c out is initially being charged, add input capacitor c1. ideally, if v1 is greater than switchover threshold v sw1 by ?v, size: c1 v sw1 ? c out ? 1C ? v 2 ? i lim ? r esr ? ? ? ? ? ? ? v (13) to ensure no switchover occurs when c out is initially be - ing charged . if the resulting c1 value causes large inrush current, is physically too big or requires a large snubber resistor when v1 is plugged in ( refer to the typical ap - plications section), select c1 to be as high a value as the application can tolerate. a filter capacitor c adj can also be added to adj to ride through the initial output charge up time. c adj should be minimized as it slows adj response, resulting in a larger output droop when the input supply powering v1 is either unplugged or drops quickly. input shorts and supply brown-out the ltc4419 temporarily turns off its active power path during input shorts or brown-out conditions if the input supply falls below out by 0.7v. if the primary input supply becomes invalid, switchover to the backup supply occurs. the power path is reactivated when the input recovers to within 0.7v of the output. figure 6 shows the response of the ltc4419 to a brown- out and recovery on v1 where switchover to v2 does not occur as v1 stays above 1.8v. when v1 falls, out gets disconnected from v1 and is slowly discharged by load resistance r out . when v1 recovers, the power path is reactivated and out tracks v1. in figure 7, when v1 falls, out gets disconnected from v1 as v1 drops below the figure?6. voltage waveforms during a brown-out on v1 that does not result in a switchover to v2. switchover threshold = 1.8v figure?7. voltage waveforms when a brown-out on v1 results in switchover to v2. switchover threshold = 3v figure?5. increasing supply hysteresis in high esr applications v1 v2 v1 v2 esr out ltc4419 r3 r8 c1 r2 out r1 cmp2 4419 f05 adj cmp1 cmpout2 cmpout1 + + c out lt c4419 4419f for more information www.linear.com/ltc4419 4419 f06 100s/div v1 5v/div v2 5v/div out 5v/div 4419 f07 c out = 10f r out = 100 c out = 10f r out = 100 100s/div v1 5v/div v2 5v/div out 5v/div
13 a pplica t ions i n f or m a t ion switch-over threshold. when v1 recovers, it needs to be qualified for 64ms before it is reconnected to out. out gets discharged by r out and is connected to v2 once its voltage is 50mv less than v2. reverse voltage blocking the ltc4419 blocks reverse voltages on supply pins v1 and v2 up to C15v relative to gnd and up to C39v relative to out. transient voltage suppressors ( tvs ) connected to v1 and v2 must be bidirectional and capacitors connected to these pins must be rated to handle reverse voltages. a reverse voltage on v2 does not disrupt v1 operation and vice versa. freshness seal freshness seal mode prevents v2 battery discharge by keeping v2 disconnected from out even if v1 is absent or invalid. very little current is drawn from v2typically just 120na. the following sequence (refer to figure 8) puts the ltc4419 in freshness seal mode: 1. power up v2 while holding v1 low and wait for at least 10ms. 2. drive v2on below 50mv. 3. power up v1 and adj for at least 94ms. freshness seal is enabled. engage this mode if v2 is a backup battery either during storage or during shipment. once freshness seal has been engaged, if v1 is disconnected , v2 stays disconnected from out. freshness seal is automatically disabled the next time v1 is revalidated. limit v2on pin capacitance to less than 10nf in order to prevent freshness seal mode from accidentally being engaged. design example in figure 9, the ltc4419 prioritizes between a 5v supply connected to v1 and a 7.4v 2- cell li-ion battery connected to v2. the system is designed to switch out to v2 when v1 drops below 4v, provide early power failure warning when v1 drops below 4.5v and low battery warning when the backup battery voltage drops below 6v. maximum anticipated load current is 100ma and maximum allowed output droop is 100mv. output rising slew rate is limited to <0.1v/ s and v1 and v2 input capacitors are limited to 10f to avoid large inrush current. 1% tolerance resistors are used. adj and cmp pin leakages are ignored as their design impact is small. first choose total resistive divider current to be ~10a for v1 and ~5a for v2. for the 5v supply, this results in: r1 + r2 + r3 = 5v 10a = 500k ? (14) since desired switchover threshold , v sw1 , and the total divider impedance are known, use equation 1 to first calculate r3. using r3 and equation 2, calculate r1 and r2. rewriting equation 1 results in: r1 + r2 ( ) = v tha ? r1 + r2 + r3 ( ) v sw1 (15) fseal enabled driven low externally 94ms 1.116v 4419 f08 1.8v 10ms 1.8v v2 v2on v1 adj 1 2 3 figure?8. freshness seal engage procedure r3 365k r2 88.7k c2 2.2f r1 44.2k r6 1m r7 1m 5v input 2-cell li-ion 7.4v r5 1.37m r sn1 0.5 r4 95.3k v1 out out pfv1 v2uv cmpout1 cmpout2 adj cmp1 cmp2 gnd 4419 f09 ltc4419 v2 c1 2.2f c out 15f + figure?9. design example lt c4419 4419f for more information www.linear.com/ltc4419
14 a pplica t ions i n f or m a t ion using ( r1 + r2 + r3 ) = 500k from equation 14, results in: r1 + r2 ( ) = 1.047v ? 500k ? 4v = 130.9k ? (16) r3 ~ (500k C 130.9k) = 369.1k ( 17) using the nearest 1% resistor value yields r3 = 365k. rearranging equation 2 results in r1 = v thc ? r2 + r2 + r3 ( ) v pfv1 (18) r1 = 0.387v 4.5v ? 500k ? ( ) (19) solving equations 16 and 19 results in r1 = 43.3k and r2 = 87.6k. using the nearest 1% resistors results in r2 = 88.7k. recalculating equation 1 using calculated r2 and r3 values and using standard 1% resistor values close to 43.3k for r1 results in r1?= 44.2k. a similar procedure is used to calculate r4 and r5 using equation 3 and total divider current. the design equations are shown below: r4 + r5 = 7.4v 5a = 1.48m ? (20) as desired current in the divider is 5a. rewriting equation 3 neglecting pin leakage and assuming r5 >> r4 results in: r4 = v thc ? r4 + r5 ( ) v v2uv (21) r4 = 0.387v ? 1.48m ? 6v (22) solving 20 and 22 results in r4 = 96. 2k and r5 = 1. 38m . choosing the nearest 1% resistor results in r4 = 95.3k and r5 = 1.37m. c out affects both out droop during switchover as deter - mined by equation 4 and out rising slew rate as determined by equation 9 . calculate minimum c out required to meet desired output droop and slew rate specifications using equations 8 and 9 and size c out to be the larger of the two values. c out required to limit out droop to < 100mv is given by equation 8: c out t pda + t switch ( ) ? i load 100mv (23) c out 7.3s + 2.5s ( ) ? 0.1a 100mv = 9.8f (24) c out required to limit out slew rate to < 0.1v/ s is given by equation 9: c out i lim 0.1v/s = 11f (25) choose a c out capacitor whose minimum value is 11f accounting for voltage and temperature coefficients. do this for other capacitors as well. assuming correct pcb layout, choose c1 to be 2.2f, which is ~ 1/5th of c out to suppress inductive transients. also snub c1 with a 0.5 resistor to prevent ringing. layout consideration make power and ground traces as wide as possible . place bypass capacitors, snubbers and tvs devices as close to the pin as possible to reduce power path resistance and parasitic inductance. these result in smaller overvoltage transients and improved overvoltage protection . place resistive dividers close to the pins to improve noise im - munity. use a 4- layer board if possible with layer 2 as dedicated gnd and solder the exposed pad to a large pcb gnd trace for better heat dissipation. a partial layout for a 2-layer pcb is shown in figure 10. lt c4419 4419f for more information www.linear.com/ltc4419
15 a pplica t ions i n f or m a t ion figure?10. recommended 12-lead mse layout for a 2-layer pcb gnd gnd c1 ltc4419 c2 gnd v1 v2 out 4419 f10 c out figure?11. maximum allowed c out vs input voltage for different t a thermal protection and maximum c out depending on the difference between input and output voltages, the ltc4419s internal power dissipation can be high when operating in current limit mode. this usually occurs when a large c out is being charged either during initial power up or when out switches over to a higher supply. the situation is made worse if a dc load is present on out , as this reduces the current available to charge c out . in such cases, self heating can cause power path turn-off due to activation of the thermal protection circuitry . the power path is reactivated when die temperature drops to a safe value. this process can repeat indefinitely if c out is discharged fully by load current i out in the interval when the power path is off. maximum allowed c out to prevent activation of the thermal protection circuit depends on several factors such as input supply and output voltages, starting ambient temperature, heat dissipation in the pcb and dc output current. choose c out < 500f if possible. if a larger c out is necessary , use figure 11 to choose c out. . follow pcb layout guidelines to improve heat dissipation. lt c4419 4419f for more information www.linear.com/ltc4419 20 100 1k 10k 60k c out (f) 4419 f11 i load = 0 ?40c 25c 85c v in (v) 5 10 15
16 typical a pplica t ions battery backup with interface to low voltage logic supercap backup with supercap charging r3 365k 5v to 18v wall adapter 3.6v to 18v backup c out 10f r2 88.7k r6 1m r7 1m r9 1m r1 44.2k r4 150k r5 1m v1 out cmpout1 cmpout2 v2on 4419 ta02 adj cmp1 cmp2 gnd ltc4419 v2 c1 10f c3 10f c2 10f in out ltc1763-3.3v shdn gnd v2on v1uv v2uv 3.3v system switchover threshold: v1 < 4v (v1 falling) v1uv threshold: v1 < 4.5v (v1 falling) v2uv threshold: v2 < 3v (v2 falling) r sn1 0.5 r sn2 0.5 r3 1m r7 1m r6 1m c out 10f switchover threshold: v1 < 4v (v1 falling) v1uv threshold: v1 < 4.4v (v1 falling) v2uv threshold: v2 < 3.5v (v2 falling) r2 237k r1 121k m1 2n4351 r4b 237k r13 127k c2: murata dmf3z5r5h474m3dta0 r12 12.1k r8 1m 1.7v to 5.5v input r4a 61.9k r5 1.87m v1 v2 out out v1uv v2uv cmpout1 l1 3.3h 4.2v c2 cmpout2 adj cmp1 v2on 4419 ta03 gnd ltc4419 cmp2 940mf 940mf c1 10f c2 120pf sw2 sw1 ltc3128 gnd v out rsenp rsens mid in prog maxv fb run lt c4419 4419f for more information www.linear.com/ltc4419
17 typical a pplica t ions triple supply monitor with primary battery pack protection early power failure warning with low battery indication + + switchover threshold: v1 < 12v (v1 falling) v2uv threshold: v2 < 7v (v2 falling) outuv threshold: out < 7.5v (out falling) r3 2m r5 2m r7 1m r6 1m c out 10f 10f r1 191k 10f r11 5.36m r10 316k 9v alkaline r4 113k 4-cell 14.8v li-ion v1 out out v2uv outuv cmp2 cmpout1 cmpout2 v2on v2on adj cmp1 4419 ta04 gnd ltc4419 v2 r3 1m r6 1m r7 1m c out 10f r2 75k r1 41.2k r5 5.23m r4 174k 4-cell 14.8v li-ion v1 out out pfv1 v2uv cmpout1 cmpout2 v2on v2on adj cmp1 cmp2 4419 ta05 gnd ltc4419 v2 c1 22f c2 10f + l1, 10h sw2 sw1 bst2 bst1 v out v in comp fb run v cc snsgnd pwm ltc3111 c3 1f c5 0.1f 12v to other circuits c4 0.1f r13 1m r14 137k c8 10f 5v to 15v input c6 39pf c7 1nf r12 44.2k r10 2.21m r11 158k pfv1 : v1 power failure threshold: v1 < 10.6v (v1 falling) switchover threshold: v1 < 10v (v1 falling) v2uv threshold: v2 < 12v (v2 falling) r8 20k c9 18pf lt c4419 4419f for more information www.linear.com/ltc4419
18 p ackage descrip t ion please refer to http://www .linear.com/product/ltc4419#packaging for the most recent package drawings. 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer lt c4419 4419f for more information www.linear.com/ltc4419
19 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . p ackage descrip t ion please refer to http://www .linear.com/product/ltc4419#packaging for the most recent package drawings. msop (mse12) 0213 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev g) lt c4419 4419f for more information www.linear.com/ltc4419
20 ? linear technology corporation 2015 lt 0816 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4419 r ela t e d p ar t s typical a pplica t ion high efficiency backup r3 1m r7 1m r6 1m c out 10f switchover threshold: v1< 4v (v1 falling) v1uv threshold: v1 < 4.4v (v1 falling) v2uv threshold: v2 < 6v (v2 falling) c3 2.2f r2 237k r1 121k r5 4.02m r4 280k 5v wall adapter 2-cell 7.4v li-ion r13 1.1m r12 1.05m v1 out v1uv v2uv cmpout1 cmpout2 v2on v2_on run 5v adj cmp1 cmp2 4419 ta06 gnd ltc4419 v2 c4 10f c2 10f c1 10f run mppc vs2 vs1 v cc bst1 bst2 sw1 pwm gnd pgnd LTC3129-1 vs3 sw2 c4 22nf c5 22nf l1 3.3h v in out system r sn1 0.5 + part number description comments lt1763 500ma, low noise micropower ldo regulators v in : 1.8v to 20v, 12-dfn, so-8 packages ltc2952 pushbutton powerpath controller with supervisor v in : 2.7v to 28v, on/off timers, 8kv hbm esd, tssop-20 and qfn-20 packages lt c3103 15v, 300ma synchronous step-down dc/dc converter v in : 2.5v-15v, dfn-10 and mse-10 packages LTC3129/LTC3129-1 15v, 200ma synchronous buck-boost dc/dc converter with 1.3a quiescent current v in : 1.92v to 15v, qfn-16 and mse-16 packages ltc3388-1/ltc3388-3 20v, 50ma high efficiency nanopower step-down regulator v in : 2.7v to 20v, dfn-10 and mse-10 packages ltc4411 2.6a low loss ideal diode in thinsot? internal 2.6a p-channel, 2.6v to 5.5v, i q = 40a, sot-23 package ltc4412 36v low loss powerpath controller in thinsot 2.5v to 36v, p-channel, i q = 11a, sot-23 package ltc4415 dual 4a ideal diodes with adjustable current limit dual internal p-channel, 1.7v to 5.5v, msop-16 and dfn-16 packages ltc4416 36v low loss dual powerpath controller for large pfets 3 .6v to 36v, 35a per i q supply, msop-10 package ltc4417 3-channel prioritized powerpath controller triple p-channel controller, 2.5v to 36v, ssop-24 and qfn-24 packages ltc4355 positive high voltage ideal diode-or with supply and fuse monitors dual n-channel, 9v to 80v, so-16, msop-16 and dfn-14 packages ltc4359 ideal diode controller with reverse input protection n-channel, 4v to 80v, msop-8 and dfn-6 packages lt c4419 4419f for more information www.linear.com/ltc4419

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